1. Field of the Invention
The present invention generally relates to a test apparatus for a semiconductor package, and more particularly to a test apparatus for a semiconductor package having a soft pad and capable of testing a multi-chip package and preventing the semiconductor package from damage.
2. Description of the Related Art
With ever increasing demands for miniaturization and higher operating speeds, multichip packages are increasingly attractive in a variety of electronics. Multichip packages that contain more than one chip can minimize volume of the system and enhance the operational speed by combining two or more chips into a single package. In addition, multichip packages decrease the interconnection length between IC chips thereby reducing signal delays and access times.
After packaging, either a single-chip package or a multi-chip must be processed with an assembly test for testing its electrical property. Conventional assembly test for a semiconductor package having array type solder balls is disclosed in U.S. Pat. No. 6,062,873 and U.S. Pat. No. 6,083,013, which are both incorporated herein by reference.
As shown in FIG. 1, U.S. Pat. No. 6,062,873 discloses a socket 10 for testing a semiconductor package 20. The semiconductor package 20 has a chip 2, a substrate 4 and a plurality of solder balls 22. The chip 2 is electrically connected to the substrate 4 by a plurality of bumps (not shown). The socket 10 includes an interposing sheet 12, a circuit substrate 14 and a socket board 16. The interposing sheet 12 has a plurality of metal traces 18 respectively corresponding to a plurality of solder balls 22 of the semiconductor package 20. The circuit substrate 14 has a plurality of metal extending pads 24 and metal bumps 26, which are disposed on the metal extending traces 24 and respectively electrically connected to the metal traces 18. The socket board 16 supports the semiconductor package 20, the interposing sheet 12 and the circuit substrate 14. The socket 10 further includes a socket body 30 and a socket lid 32, wherein the socket body 30 supports the socket board 16 and the socket lid 32 is disposed over the interposing sheet 12. The socket lid 32 and the interposing sheet 12 define a space for receiving the semiconductor package 20. When the socket lid 32 presses the semiconductor package 20, the solder balls 22 are respectively electrically connected to the metal bumps 26. The socket body 30 has a plurality of contact pins 42 for electrically connecting the metal extending traces 24 to an external electrical device (not shown), thereby testing the electrical property of the semiconductor package 20.
Furthermore, U.S. Pat. No. 6,062,873 discloses an integral circuit (IC) socket, which includes a socket body, a plurality of bow-shaped contact pins and a socket lid. The socket supports the bow-shaped contact pins. A floating member is provided with a plurality of holes for guiding the upper portions of the bow-shaped contact pins. The integral circuit is put on the floating member. When the socket lid presses the integral circuit, the upper portions of the bow-shaped contact pins are respectively electrically connected to a plurality of solder balls of the integral circuit, and the lower portions of the bow-shaped contact pins are electrically connected to an external electrical device (not shown), thereby testing the electrical property of the integral circuit.
However, the above-mentioned socket of conventional test apparatus for a semiconductor package is only applied to a single chip package having a surface with better evenness condition. As shown in FIG. 2, a multi-chip package 70 mainly includes a plurality of chips 52a, 52b, a substrate 54, a plurality of solder balls 72 and a plurality of bumps 56. When the above-mentioned socket is applied to the multi-chip package 70, the chips 52a, 52b of the multi-chip package 70 are not located on the same horizontal plane, i.e., the multi-chip package 70 has a surface with worse evenness condition, and therefore the socket usually generates the bigger force which is focused on the chip with higher height so as to damage the multi-chip package 70 during assembly test. Otherwise, the above-mentioned conventional test apparatus for a semiconductor package also causes the solder balls 72 or the bumps 56 to crack and further decreases the reliability of the multi-chip package.
Accordingly, there exists a need for a test apparatus for a semiconductor package capable of solving the above-mentioned disadvantage.